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Exam 2

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Your quiz has been submitted successfully. Question 1 | | 0 / 2 points |
The maxterm expression for the function g(A,B,C) given: g(A,B,C) = A'B + BC + AB'C | | a) | ∏M(2,3,5,7) | | | | b) | ∏M(0,1,6) | | | | c) | ∏M(0,1,4,6) | | | | d) | None of the above | | Question 2 | | 0 / 4 points |
For the function: f(A,B,C,D) = A'B + BC'D'
What would be the canonical sum of products expansion? | | a) | f(A,B,C,D)= A'BC'D'+A'BC'D+A'BCD'+ A'BCD + AB'CD'+ABCD'+ ABCD | | | | b) | f(A,B,C,D)= A'BC'D'+A'BC'D+A'BCD'+ A'BCD + ABC'D' | | | | c) | f(A,B,C,D)= A'BC'D'+C'D+A'BCD'+ A'BCD + ABC'D'+ BC'D+BCD'+ CD | | | | d) | The function is already expressed in canonical form | | Question 3 | | 3 / 3 points |
The simplified product-of-sums expressions may be easily implemented into actual logic circuits using all ________ with little or no increase in circuit complexity. | | OR gates | | | AND gates | | | NOR gates | | | multiple-input inverters | Question 4 | | 2 / 2 points |
Simplifying logic circuits results in: | | fewer potential faults. | | | fewer connections. | | | fewer gates. | | | all of the above | Question 5 | | 0 / 3 points |
Given F1 = Π M(0, 4, 5, 6) and F2 = Π M(0, 4, 7) the maxterm expression for F1F2 is: | | F1F2 = Π M(0, 4, 5, 6, 7) | | | F1F2 = Π M(1, 2, 3) | | | F1F2 = Π M(0, 4) | | | None of the above | Question 6 | | 0 / 4 points |
A combinational logic circuit which has one output Z and 4-bit input ABCD representing a binary number. Z should be 1 if and only if the input is at least 5 (ABCD = 0101), but is not greater than 11 (ABCD = 1011). What is the minimum solution for Z(A,B,C,D) given in sum-of-product? | | Z(A,B,C,D) = AB’ + A’BD + A’BCD’ + A’BC | | | Z(A,B,C,D) = AB’ + A’D + A’D’ + A’BC | | | Z(A,B,C,D) = AB’ + A’BD + A’BC | | | None of the above | Question 7 | | 3 / 3 points |
The symbol for a flip flop has a small triangle - and no bubble - on its clock (CLK) input. The triangle indicates: | | the FF is level active and can only change states when the CLOCK = 1. | | | the FF is edge-triggered and can only change states when the clock goes from 1 to 0. | | | the FF is an active LOW device and can only change states when the CLOCK = 0. | | | the FF is edge-triggered and can only change states when the clock goes 0 to 1. | Question 8 | | 0 / 4 points |

For the karnaugh map in the figure which option correspond to the minimal solution? | | a) | Option a) | | | | b) | Option b) | | | | c) | Option c) | | | | d) | Option d) | | | | e) | None of the above | | Question 9 | | 0 / 3 points |
Select the statement that best describes the use of "Don't Care" conditions on a K-map. | | Don't Care conditions may be changed to either a 0 or a 1. | | | Don't Care conditions should never occur and should not be included in K-map simplification procedures. | | | Don't Care conditions may only be changed to 1s. | | | Don't Care conditions may only be changed to 0s. | Question 10 | | 3 / 3 points |
Which of the following is not generally associated with flip-flops? | | Interval time | | | Hold time | | | Set-up time | | | Propagation delay time | Question 11 | | 3 / 3 points |
Set-up time specifies ________. | | the minimum time for the control levels to be maintained on the inputs prior to the triggering edge of the clock in order for data to be reliably clocked into the FF | | | how long the operator has in order to get the flip-flop running before the maximum power level is exceeded | | | how long it takes the output to change states after the clock has transitioned | | | the maximum time interval required for the control levels to remain on the inputs before the triggering edge of the clock in order for the data to be reliably clocked out of the FF | Question 12 | | 3 / 3 points |
As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be: | | very short. | | | of no consequence as long as the levels are within the determinate range of values. | | | very long. | | | at a maximum value to enable the input control signals to stabilize. | Question 13 | | 3 / 3 points |
Flip-flops are normally used for all of the following applications, except ________. | | counting | | | frequency division | | | logic gates | | | data storage | Question 14 | | 0 / 3 points |
A J-K flip-flop is being used as a divide-by-2 circuit when ________. | | the J and K inputs are tied to ground (logic '0') | | | the reset is tied to the clock | | | the J and K inputs are tied to Vcc (logic '1') | | | all the inputs are connected to the preset | Question 15 | | 3 / 3 points |

In the figure above if R=0; S=1 then the output Q is? | | a) | Q = 1 | | | | b) | Q = 0 | | | | c) | Depends on the value of Q before setting R and S | | | | d) | Imposible to know | | Question 16 | | 3 / 3 points |
A primary difference between a clocked J-K flip-flop and a clocked S-R flip-flop is the J-K's ability to: | | Toggle or change states when J = 1, K = 1, and a clock transition occurs. | | | Always reset to the CLEAR state when J = 1, K = 1, and a clock transition occurs. | | | Remain in the CLEAR state when J = 1, K = 0, and a clock transition occurs. | | | Always reset to the set state when J = 1, K = 1, and a clock transition occurs. | Question 17 | | 3 / 3 points |
Which of the following circuit parameters would be most likely to limit the maximum operating frequency of an IC flip-flop? | | Propagation delay time | | | Clock pulse HIGH and LOW time | | | Set-up and hold time | | | Clock transition time | Question 18 | | 0 / 3 points |
The asynchronous transfer of data between J-K storage registers can easily be accomplished using the: | | Clock and the input J-K control signals. | | | J-K control signals only. | | | Clock with the PRESET and CLEAR inputs. | | | PRESET and CLEAR inputs only. | Question 19 | | 3 / 3 points |
Which statement best describes the operation of a Negative-Edge-triggered D flip-flop? | | The Q output is always identical to the D input. | | | The Q output is always identical to the D input when CLK makes a low-to-high transition. | | | The Q output is always identical to the CLK input if the D input is HIGH. | | | The logic level at the D input is transferred to Q on high-to-low transition of CLK. | Question 20 | | 0 / 4 points |

For the circuit, and the corresponding waveform showed above, what are the values of Q at times t1, t2, t3, t4 and t5? | | a) | 0, 1, 1 ,0, 0 | | | | b) | 0, 1, 0, 0, 0 | | | | c) | 0, 1, 0, 0, 1 | | | | d) | None of above | | Question 21 | | 0 / 3 points |
What would be the sequence of outputs of a JK Flip-Flop if J=0 and K=1 for the first clock pulse and then J=1 and K=1 for the next 3 clock pulses? | | 1010 | | | 0101 | | | 1101 | | | None of the above | Question 22 | | 0 / 4 points |

For the circuit of the figure above, if the circuit is fed with the waveform given, what are the values of Q for times t1,t2 and t3 respectively? | | a) | 0,0,1 | | | | b) | 1,1,0 | | | | c) | 0,0,0 | | | | d) | 0,1,1 | | Question 23 | | 0 / 4 points |

For the function f(x1,x2,x3,x4) given above as minterm expression, which option represents the simplified version of f? | | a) | Option a) | | | | b) | Option b) | | | | c) | Option c) | | | | d) | Option d) | | | | e) | None of the above | | Question 24 | | 0 / 3 points |
The function F(A,B,C,D) = ∑(0,1,4, 5) could be implemented with a minimum cost using: | | One inverter | | | Two two-inputs AND gate and one two two-inputs OR gate | | | One two-inputs NAND gates | | | One two-inputs NOR gate | | | None of the above | Question 25 | | 0 / 4 points |

The figure above shows a waveform for the inputs of a JK flip-flop falling-edge-triggering with PRESET and CLEAR. What are the values of the flip-flop output for the times shown in t2, t4, t6, t7 and t8 respectively? | | 1, 1, 1, 1, 0 | | | 0, 1, 1, 1, 0 | | | 0, 1, 1, 0, 1 | | | None of the above |
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